The present invention relates to a semiconductor design technology, and particularly, to a semiconductor memory device which operates at high speed. More particularly, the present invention relates to a device and method, which perform crossing-point training (i.e., vix training) between data clocks that are inputted as differential signals, in a high-speed semiconductor memory device.
In a system including a plurality of semiconductor memory devices, a semiconductor memory device stores data. When a data processing device, for example, a memory controller unit (MCU), requests data, the semiconductor memory device outputs data corresponding to an address which is inputted from the data-requesting device or stores data, which are provided from the data-requesting device, in a location corresponding to the address.
As such, a recently developed high-speed memory device was designed to input/output two bits of data at the rising edge and falling edge of an external system clock and to input/output two bits of data at a falling edge and the next rising edge. That is, the high-speed memory device is designed to input/output four bits of data during one cycle of a system clock.
However, because the system clock is represented only in two logic states, i.e., a logic high level and a logic low level, the high-speed memory device requires a data clock with a frequency that is two times faster than that of the system clock for inputting/outputting four bits of data during one cycle. That is, a dedicated clock is required for inputting/outputting data.
Accordingly, a high-speed semiconductor memory device uses a system clock as a reference clock when transmitting/receiving an address and a command. When inputting/outputting data, by using a data clock as the reference clock, the high-speed semiconductor memory device controls the data clock to have a frequency two times faster than that of the system clock.
That is, the high-speed semiconductor memory device allows two cycles of the data clock to be achieved during one cycle of the system clock, and allows the input/output of data to occur at the rising edge and falling edge of the data clock, thereby enabling four bits of data to be inputted/outputted during one cycle of the system clock.
Unlike a typical Double Data Rate (DDR) synchronous memory device that uses one system clock as a reference clock for performing a read/writing operation, the high-speed semiconductor memory device transfers/receives data by using two clocks having different frequencies for performing a read/writing operation.
As described above, a data clock has a relatively high frequency that is two times higher than the frequency of a system clock. Because the data clock thus has a relatively high frequency, the phase of the data clock may be highly distorted by noise generated at the transmission stage of the data clock. In addressing this, when transmitting a data clock, the high-speed semiconductor memory device uses a method that divides the data clock into two out-of-phase data clocks and transmits the data clock differentially.
By transmitting the data clock differentially, much noise-induced distortion in the data clock has been resolved to some degree. However, a method of transmitting the data clock differentially transmits two out-of-phase data clocks simultaneously through different transmission lines, and thus the two transmitted clocks may not have opposite phases with respect to each other as desired. That is, due to the minute resistance difference between transmission lines through which the respective data clocks are transmitted or peripheral environments, two data clocks may adopt different phase shifts while being transmitted. Accordingly, although the two data clocks may have opposite phases with respect to each other at the point when transmission is begun from an MCU, they may not maintain the opposite phases at the arrival point when the two data clocks arrive at a semiconductor memory device at the end of the transmission.